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dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195
To support reset of infra_ao, add the index of infra_ao reset of thermal/svs/pcei for MT8192 and thermal/svs for MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-14-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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committed by
Stephen Boyd
parent
4d352eb91a
commit
fb91526b5f
@@ -7,6 +7,7 @@
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
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/* TOPRGU resets */
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#define MT8192_TOPRGU_MM_SW_RST 1
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#define MT8192_TOPRGU_MFG_SW_RST 2
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#define MT8192_TOPRGU_VENC_SW_RST 3
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@@ -30,4 +31,11 @@
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/* MMSYS resets */
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#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
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/* INFRA resets */
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#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0
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#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1
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#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2
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#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3
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#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
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@@ -7,6 +7,7 @@
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
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/* TOPRGU resets */
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#define MT8195_TOPRGU_CONN_MCU_SW_RST 0
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#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
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#define MT8195_TOPRGU_APU_SW_RST 2
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@@ -26,4 +27,9 @@
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#define MT8195_TOPRGU_SW_RST_NUM 16
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/* INFRA resets */
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#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
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#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
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#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
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