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Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E 64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=y. To support unified kernel Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus it brings some bad effects to coherent platforms: Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and kmalloc-8 slab caches don't exist any more, they are replaced with either kmalloc-128 or kmalloc-64. Secondly, larger than necessary kmalloc aligned allocations results in unnecessary cache/TLB pressure. This issue also exists on arm64 platforms. From last year, Catalin tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage in various drivers with ARCH_DMA_MINALIGN etc.[1] One fact we can make use of for riscv: if the CPU doesn't support ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on Catalin's work and above fact, we can easily solve the kmalloc align issue for riscv: we can override dma_get_cache_alignment(), then let it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know the underlying HW neither supports ZICBOM nor supports T-HEAD CMO. So what about if the CPU supports ZICBOM or T-HEAD CMO, but all the devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the kmalloc minimum alignment, nothing changed in this case. This case can be improved in the future. After this patch, a simple test of booting to a small buildroot rootfs on qemu shows: kmalloc-96 5041 5041 96 ... kmalloc-64 9606 9606 64 ... kmalloc-32 5128 5128 32 ... kmalloc-16 7682 7682 16 ... kmalloc-8 10246 10246 8 ... So we save about 1268KB memory. The saving will be much larger in normal OS env on real HW platforms. Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/ [1] Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230718152214.2907-2-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
89 lines
2.2 KiB
C
89 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* RISC-V specific functions to support DMA for non-coherent devices
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*/
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#include <linux/dma-direct.h>
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#include <linux/dma-map-ops.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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static bool noncoherent_supported __ro_after_init;
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int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
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EXPORT_SYMBOL_GPL(dma_cache_alignment);
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_TO_DEVICE:
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ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
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break;
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case DMA_FROM_DEVICE:
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ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
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break;
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case DMA_BIDIRECTIONAL:
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ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
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break;
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default:
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break;
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}
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}
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_TO_DEVICE:
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break;
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
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break;
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default:
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break;
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}
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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void *flush_addr = page_address(page);
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ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
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}
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN,
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TAINT_CPU_OUT_OF_SPEC,
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"%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)",
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dev_driver_string(dev), dev_name(dev),
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ARCH_DMA_MINALIGN, riscv_cbom_block_size);
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WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC,
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"%s %s: device non-coherent but no non-coherent operations supported",
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dev_driver_string(dev), dev_name(dev));
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dev->dma_coherent = coherent;
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}
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void riscv_noncoherent_supported(void)
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{
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WARN(!riscv_cbom_block_size,
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"Non-coherent DMA support enabled without a block size\n");
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noncoherent_supported = true;
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}
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void __init riscv_set_dma_cache_alignment(void)
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{
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if (!noncoherent_supported)
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dma_cache_alignment = 1;
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}
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