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Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next

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- Remove OXNAS clk driver

* clk-bindings:
  dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml
  dt-bindings: clock: xlnx,versal-clk: drop select:false
  dt-bindings: clock: versal: Add versal-net compatible string
  dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
  dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding

* clk-starfive:
  reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
  clk: starfive: Simplify .determine_rate()
  clk: starfive: Add StarFive JH7110 Video-Output clock driver
  clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
  clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
  clk: starfive: jh7110-sys: Add PLL clocks source from DTS
  clk: starfive: Add StarFive JH7110 PLL clock driver
  dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
  dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
  dt-bindings: soc: starfive: Add StarFive syscon module
  dt-bindings: clock: Add StarFive JH7110 PLL clock generator

* clk-rm:
  dt-bindings: clk: oxnas: remove obsolete bindings
  clk: oxnas: remove obsolete clock driver

* clk-renesas:
  clk: renesas: rcar-gen3: Add ADG clocks
  clk: renesas: r8a77965: Add 3DGE and ZG support
  clk: renesas: r8a7796: Add 3DGE and ZG support
  clk: renesas: r8a7795: Add 3DGE and ZG support
  clk: renesas: emev2: Remove obsolete clkdev registration
  clk: renesas: r9a07g043: Add MTU3a clock and reset entry
  clk: renesas: rzg2l: Simplify .determine_rate()
  clk: renesas: r9a09g011: Add CSI related clocks
  clk: renesas: r8a774b1: Add 3DGE and ZG support
  clk: renesas: r8a774e1: Add 3DGE and ZG support
  clk: renesas: r8a774a1: Add 3DGE and ZG support
  clk: renesas: rcar-gen3: Add support for ZG clock

* clk-cleanup:
  clk: mvebu: Convert to devm_platform_ioremap_resource()
  clk: nuvoton: Convert to devm_platform_ioremap_resource()
  clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
  clk: ti: Use devm_platform_get_and_ioremap_resource()
  clk: mediatek: Convert to devm_platform_ioremap_resource()
  clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
  clk: gemini: Convert to devm_platform_ioremap_resource()
  clk: fsl-sai: Convert to devm_platform_ioremap_resource()
  clk: bm1880: Convert to devm_platform_ioremap_resource()
  clk: axm5516: Convert to devm_platform_ioremap_resource()
  clk: actions: Convert to devm_platform_ioremap_resource()
  clk: cdce925: Remove redundant of_match_ptr()
  drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()
  clk: Explicitly include correct DT includes
This commit is contained in:
Stephen Boyd
2023-08-30 14:37:45 -07:00
parent 03d4a10040 0e2b2a7627 096110aa23 772b455987 0a26c3f8e0
commit d10ebc7c64
249 changed files with 2093 additions and 667 deletions
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80
include/dt-bindings/clock/starfive,jh7110-crg.h
View File

@@ -1,11 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
* Copyright 2022 StarFive Technology Co., Ltd.
*/
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
/* PLL clocks */
#define JH7110_PLLCLK_PLL0_OUT 0
#define JH7110_PLLCLK_PLL1_OUT 1
#define JH7110_PLLCLK_PLL2_OUT 2
#define JH7110_PLLCLK_END 3
/* SYSCRG clocks */
#define JH7110_SYSCLK_CPU_ROOT 0
#define JH7110_SYSCLK_CPU_CORE 1
@@ -218,4 +225,77 @@
#define JH7110_AONCLK_END 14
/* STGCRG clocks */
#define JH7110_STGCLK_HIFI4_CLK_CORE 0
#define JH7110_STGCLK_USB0_APB 1
#define JH7110_STGCLK_USB0_UTMI_APB 2
#define JH7110_STGCLK_USB0_AXI 3
#define JH7110_STGCLK_USB0_LPM 4
#define JH7110_STGCLK_USB0_STB 5
#define JH7110_STGCLK_USB0_APP_125 6
#define JH7110_STGCLK_USB0_REFCLK 7
#define JH7110_STGCLK_PCIE0_AXI_MST0 8
#define JH7110_STGCLK_PCIE0_APB 9
#define JH7110_STGCLK_PCIE0_TL 10
#define JH7110_STGCLK_PCIE1_AXI_MST0 11
#define JH7110_STGCLK_PCIE1_APB 12
#define JH7110_STGCLK_PCIE1_TL 13
#define JH7110_STGCLK_PCIE_SLV_MAIN 14
#define JH7110_STGCLK_SEC_AHB 15
#define JH7110_STGCLK_SEC_MISC_AHB 16
#define JH7110_STGCLK_GRP0_MAIN 17
#define JH7110_STGCLK_GRP0_BUS 18
#define JH7110_STGCLK_GRP0_STG 19
#define JH7110_STGCLK_GRP1_MAIN 20
#define JH7110_STGCLK_GRP1_BUS 21
#define JH7110_STGCLK_GRP1_STG 22
#define JH7110_STGCLK_GRP1_HIFI 23
#define JH7110_STGCLK_E2_RTC 24
#define JH7110_STGCLK_E2_CORE 25
#define JH7110_STGCLK_E2_DBG 26
#define JH7110_STGCLK_DMA1P_AXI 27
#define JH7110_STGCLK_DMA1P_AHB 28
#define JH7110_STGCLK_END 29
/* ISPCRG clocks */
#define JH7110_ISPCLK_DOM4_APB_FUNC 0
#define JH7110_ISPCLK_MIPI_RX0_PXL 1
#define JH7110_ISPCLK_DVP_INV 2
#define JH7110_ISPCLK_M31DPHY_CFG_IN 3
#define JH7110_ISPCLK_M31DPHY_REF_IN 4
#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5
#define JH7110_ISPCLK_VIN_APB 6
#define JH7110_ISPCLK_VIN_SYS 7
#define JH7110_ISPCLK_VIN_PIXEL_IF0 8
#define JH7110_ISPCLK_VIN_PIXEL_IF1 9
#define JH7110_ISPCLK_VIN_PIXEL_IF2 10
#define JH7110_ISPCLK_VIN_PIXEL_IF3 11
#define JH7110_ISPCLK_VIN_P_AXI_WR 12
#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13
#define JH7110_ISPCLK_END 14
/* VOUTCRG clocks */
#define JH7110_VOUTCLK_APB 0
#define JH7110_VOUTCLK_DC8200_PIX 1
#define JH7110_VOUTCLK_DSI_SYS 2
#define JH7110_VOUTCLK_TX_ESC 3
#define JH7110_VOUTCLK_DC8200_AXI 4
#define JH7110_VOUTCLK_DC8200_CORE 5
#define JH7110_VOUTCLK_DC8200_AHB 6
#define JH7110_VOUTCLK_DC8200_PIX0 7
#define JH7110_VOUTCLK_DC8200_PIX1 8
#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
#define JH7110_VOUTCLK_DSITX_APB 10
#define JH7110_VOUTCLK_DSITX_SYS 11
#define JH7110_VOUTCLK_DSITX_DPI 12
#define JH7110_VOUTCLK_DSITX_TXESC 13
#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
#define JH7110_VOUTCLK_HDMI_TX_SYS 17
#define JH7110_VOUTCLK_END 18
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */

60
include/dt-bindings/reset/starfive,jh7110-crg.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
@@ -151,4 +152,63 @@
#define JH7110_AONRST_END 8
/* STGCRG resets */
#define JH7110_STGRST_SYSCON 0
#define JH7110_STGRST_HIFI4_CORE 1
#define JH7110_STGRST_HIFI4_AXI 2
#define JH7110_STGRST_SEC_AHB 3
#define JH7110_STGRST_E24_CORE 4
#define JH7110_STGRST_DMA1P_AXI 5
#define JH7110_STGRST_DMA1P_AHB 6
#define JH7110_STGRST_USB0_AXI 7
#define JH7110_STGRST_USB0_APB 8
#define JH7110_STGRST_USB0_UTMI_APB 9
#define JH7110_STGRST_USB0_PWRUP 10
#define JH7110_STGRST_PCIE0_AXI_MST0 11
#define JH7110_STGRST_PCIE0_AXI_SLV0 12
#define JH7110_STGRST_PCIE0_AXI_SLV 13
#define JH7110_STGRST_PCIE0_BRG 14
#define JH7110_STGRST_PCIE0_CORE 15
#define JH7110_STGRST_PCIE0_APB 16
#define JH7110_STGRST_PCIE1_AXI_MST0 17
#define JH7110_STGRST_PCIE1_AXI_SLV0 18
#define JH7110_STGRST_PCIE1_AXI_SLV 19
#define JH7110_STGRST_PCIE1_BRG 20
#define JH7110_STGRST_PCIE1_CORE 21
#define JH7110_STGRST_PCIE1_APB 22
#define JH7110_STGRST_END 23
/* ISPCRG resets */
#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
#define JH7110_ISPRST_M31DPHY_HW 2
#define JH7110_ISPRST_M31DPHY_B09_AON 3
#define JH7110_ISPRST_VIN_APB 4
#define JH7110_ISPRST_VIN_PIXEL_IF0 5
#define JH7110_ISPRST_VIN_PIXEL_IF1 6
#define JH7110_ISPRST_VIN_PIXEL_IF2 7
#define JH7110_ISPRST_VIN_PIXEL_IF3 8
#define JH7110_ISPRST_VIN_SYS 9
#define JH7110_ISPRST_VIN_P_AXI_RD 10
#define JH7110_ISPRST_VIN_P_AXI_WR 11
#define JH7110_ISPRST_END 12
/* VOUTCRG resets */
#define JH7110_VOUTRST_DC8200_AXI 0
#define JH7110_VOUTRST_DC8200_AHB 1
#define JH7110_VOUTRST_DC8200_CORE 2
#define JH7110_VOUTRST_DSITX_DPI 3
#define JH7110_VOUTRST_DSITX_APB 4
#define JH7110_VOUTRST_DSITX_RXESC 5
#define JH7110_VOUTRST_DSITX_SYS 6
#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
#define JH7110_VOUTRST_DSITX_TXESC 8
#define JH7110_VOUTRST_HDMI_TX_HDMI 9
#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
#define JH7110_VOUTRST_END 12
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */