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dt-bindings: clock: qcom: Add SM8550 graphics clock controller

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Add device tree bindings for the graphics clock controller on
Qualcomm SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com
This commit is contained in:
Jagadeesh Kona
2023-05-24 23:47:58 +05:30
committed by Bjorn Andersson
parent 63f4e4b6f5
commit 778af143ad
2 changed files with 50 additions and 0 deletions
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2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
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@@ -15,12 +15,14 @@ description: |
See also:: See also::
include/dt-bindings/clock/qcom,sm8450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h
properties: properties:
compatible: compatible:
enum: enum:
- qcom,sm8450-gpucc - qcom,sm8450-gpucc
- qcom,sm8550-gpucc
clocks: clocks:
items: items:

48
include/dt-bindings/clock/qcom,sm8550-gpucc.h Normal file
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@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CRC_AHB_CLK 1
#define GPU_CC_CX_FF_CLK 2
#define GPU_CC_CX_GMU_CLK 3
#define GPU_CC_CXO_AON_CLK 4
#define GPU_CC_CXO_CLK 5
#define GPU_CC_DEMET_CLK 6
#define GPU_CC_DEMET_DIV_CLK_SRC 7
#define GPU_CC_FF_CLK_SRC 8
#define GPU_CC_FREQ_MEASURE_CLK 9
#define GPU_CC_GMU_CLK_SRC 10
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11
#define GPU_CC_HUB_AON_CLK 12
#define GPU_CC_HUB_CLK_SRC 13
#define GPU_CC_HUB_CX_INT_CLK 14
#define GPU_CC_MEMNOC_GFX_CLK 15
#define GPU_CC_MND1X_0_GFX3D_CLK 16
#define GPU_CC_MND1X_1_GFX3D_CLK 17
#define GPU_CC_PLL0 18
#define GPU_CC_PLL1 19
#define GPU_CC_SLEEP_CLK 20
#define GPU_CC_XO_CLK_SRC 21
#define GPU_CC_XO_DIV_CLK_SRC 22
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
/* GPU_CC resets */
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CX_BCR 1
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
#define GPUCC_GPU_CC_FF_BCR 3
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
#define GPUCC_GPU_CC_GMU_BCR 5
#define GPUCC_GPU_CC_GX_BCR 6
#define GPUCC_GPU_CC_XO_BCR 7
#endif