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perf: RISC-V: Define helper functions expose hpm counter width and count
KVM module needs to know how many hardware counters and the counter width that the platform supports. Otherwise, it will not be able to show optimal value of virtual counters to the guest. The virtual hardware counters also need to have the same width as the logical hardware counters for simplicity. However, there shouldn't be mapping between virtual hardware counters and logical hardware counters. As we don't support hetergeneous harts or counters with different width as of now, the implementation relies on the counter width of the first available programmable counter. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
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@@ -73,6 +73,9 @@ void riscv_pmu_legacy_skip_init(void);
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static inline void riscv_pmu_legacy_skip_init(void) {};
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#endif
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struct riscv_pmu *riscv_pmu_alloc(void);
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#ifdef CONFIG_RISCV_PMU_SBI
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int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr);
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#endif
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#endif /* CONFIG_RISCV_PMU */
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