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Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'clk-lmk' into clk-next

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- Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
 - Remove non-OF mmp clk drivers
 - Move number of clks from DT headers to drivers

* clk-imx:
  clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
  clk: imx: pll14xx: align pdiv with reference manual
  clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
  clk: imx25: make __mx25_clocks_init return void
  clk: imx25: print silicon revision during init
  dt-bindings: clocks: imx8mp: make sai4 a dummy clock
  clk: imx8mp: fix sai4 clock
  clk: imx: imx8ulp: update SPLL2 type
  clk: imx: pllv4: Fix SPLL2 MULT range
  clk: imx: imx8: add audio clock mux driver
  dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
  clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
  clk: imx: clk-gpr-mux: Simplify .determine_rate()
  clk: imx: Add 519.75MHz frequency support for imx9 pll
  clk: imx93: Add PDM IPG clk
  dt-bindings: clock: imx93: Add PDM IPG clk

* clk-samsung:
  dt-bindings: clock: samsung: remove define with number of clocks
  clk: samsung: exynoautov9: do not define number of clocks in bindings
  clk: samsung: exynos850: do not define number of clocks in bindings
  clk: samsung: exynos7885: do not define number of clocks in bindings
  clk: samsung: exynos5433: do not define number of clocks in bindings
  clk: samsung: exynos5420: do not define number of clocks in bindings
  clk: samsung: exynos5410: do not define number of clocks in bindings
  clk: samsung: exynos5260: do not define number of clocks in bindings
  clk: samsung: exynos5250: do not define number of clocks in bindings
  clk: samsung: exynos4: do not define number of clocks in bindings
  clk: samsung: exynos3250: do not define number of clocks in bindings

* clk-annotate:
  clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by
  clk: Annotate struct clk_hw_onecell_data with __counted_by

* clk-marvell:
  clk: pxa910: Move number of clocks to driver source
  clk: pxa1928: Move number of clocks to driver source
  clk: pxa168: Move number of clocks to driver source
  clk: mmp2: Move number of clocks to driver source
  clk: mmp: Remove old non-OF clock drivers

* clk-lmk:
  clk: lmk04832: Support using PLL1_LD as SPI readback pin
  clk: lmk04832: Don't disable vco clock on probe fail
  clk: lmk04832: Set missing parent_names for output clocks
This commit is contained in:
Stephen Boyd
2023-08-30 14:39:19 -07:00
parent 032bcf783e 960535d54f e5546e9136 a5be6db5a2 3b99cd274e 6aa8dc690d
commit 3462100cf3
67 changed files with 1057 additions and 1438 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
include/dt-bindings/clock/exynos3250.h
View File

@@ -256,12 +256,6 @@
#define CLK_SCLK_UART2 248
#define CLK_SCLK_MMC2 249
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define CLK_NR_CLKS 250
/*
* CMU DMC
*/
@@ -283,12 +277,6 @@
#define CLK_DIV_DMCP 19
#define CLK_DIV_DMCD 20
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define NR_CLKS_DMC 21
/*
* CMU ISP
*/
@@ -344,10 +332,4 @@
#define CLK_ASYNCAXIM 46
#define CLK_SCLK_MPWM_ISP 47
/*
* Total number of clocks of CMU_ISP.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define NR_CLKS_ISP 48
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

5
include/dt-bindings/clock/exynos4.h
View File

@@ -239,9 +239,6 @@
#define CLK_DIV_GDR 460
#define CLK_DIV_CORE2 461
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 462
/* Exynos4x12 ISP clocks */
#define CLK_ISP_FIMC_ISP 1
#define CLK_ISP_FIMC_DRC 2
@@ -275,6 +272,4 @@
#define CLK_ISP_DIV_MCUISP0 29
#define CLK_ISP_DIV_MCUISP1 30
#define CLK_NR_ISP_CLKS 31
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */

3
include/dt-bindings/clock/exynos5250.h
View File

@@ -177,7 +177,4 @@
#define CLK_MOUT_MPLL 1029
#define CLK_MOUT_VPLLSRC 1030
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 1031
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */

25
include/dt-bindings/clock/exynos5260-clk.h
View File

@@ -137,8 +137,6 @@
#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122
#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123
#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124
#define TOP_NR_CLK 125
/* List Of Clocks For CMU_EGL */
@@ -153,8 +151,6 @@
#define EGL_DOUT_ACLK_EGL 9
#define EGL_DOUT_EGL2 10
#define EGL_DOUT_EGL1 11
#define EGL_NR_CLK 12
/* List Of Clocks For CMU_KFC */
@@ -168,8 +164,6 @@
#define KFC_DOUT_KFC_ATCLK 8
#define KFC_DOUT_KFC2 9
#define KFC_DOUT_KFC1 10
#define KFC_NR_CLK 11
/* List Of Clocks For CMU_MIF */
@@ -200,8 +194,6 @@
#define MIF_CLK_INTMEM 25
#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26
#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27
#define MIF_NR_CLK 28
/* List Of Clocks For CMU_G3D */
@@ -211,8 +203,6 @@
#define G3D_DOUT_ACLK_G3D 4
#define G3D_CLK_G3D_HPM 5
#define G3D_CLK_G3D 6
#define G3D_NR_CLK 7
/* List Of Clocks For CMU_AUD */
@@ -231,8 +221,6 @@
#define AUD_SCLK_AUD_UART 13
#define AUD_SCLK_PCM 14
#define AUD_SCLK_I2S 15
#define AUD_NR_CLK 16
/* List Of Clocks For CMU_MFC */
@@ -241,8 +229,6 @@
#define MFC_CLK_MFC 3
#define MFC_CLK_SMMU2_MFCM1 4
#define MFC_CLK_SMMU2_MFCM0 5
#define MFC_NR_CLK 6
/* List Of Clocks For CMU_GSCL */
@@ -272,8 +258,6 @@
#define GSCL_CLK_SMMU3_MSCL1 24
#define GSCL_SCLK_CSIS1_WRAP 25
#define GSCL_SCLK_CSIS0_WRAP 26
#define GSCL_NR_CLK 27
/* List Of Clocks For CMU_FSYS */
@@ -295,8 +279,6 @@
#define FSYS_CLK_SMMU_RTIC 16
#define FSYS_PHYCLK_USBDRD30 17
#define FSYS_PHYCLK_USBHOST20 18
#define FSYS_NR_CLK 19
/* List Of Clocks For CMU_PERI */
@@ -366,8 +348,6 @@
#define PERI_SCLK_SPDIF 64
#define PERI_SCLK_I2S 65
#define PERI_SCLK_PCM1 66
#define PERI_NR_CLK 67
/* List Of Clocks For CMU_DISP */
@@ -406,8 +386,6 @@
#define DISP_CLK_DP 33
#define DISP_SCLK_PIXEL 34
#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35
#define DISP_NR_CLK 36
/* List Of Clocks For CMU_G2D */
@@ -423,8 +401,6 @@
#define G2D_CLK_SMMU_SSS 10
#define G2D_CLK_SMMU_MDMA 11
#define G2D_CLK_SMMU3_G2D 12
#define G2D_NR_CLK 13
/* List Of Clocks For CMU_ISP */
@@ -461,6 +437,5 @@
#define ISP_SCLK_SPI0_EXT 31
#define ISP_SCLK_SPI1_EXT 32
#define ISP_SCLK_UART_EXT 33
#define ISP_NR_CLK 34
#endif

2
include/dt-bindings/clock/exynos5410.h
View File

@@ -61,6 +61,4 @@
#define CLK_USBD301 367
#define CLK_SSS 471
#define CLK_NR_CLKS 512
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */

3
include/dt-bindings/clock/exynos5420.h
View File

@@ -271,7 +271,4 @@
#define CLK_DOUT_PCLK_DREX0 798
#define CLK_DOUT_PCLK_DREX1 799
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 800
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */

42
include/dt-bindings/clock/exynos5433.h
View File

@@ -188,8 +188,6 @@
#define CLK_SCLK_ISP_SPI0_CAM1 252
#define CLK_SCLK_HDMI_SPDIF_DISP 253
#define TOP_NR_CLK 254
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -200,8 +198,6 @@
#define CLK_SCLK_MPHY_PLL 11
#define CLK_SCLK_UFS_MPHY 11
#define CPIF_NR_CLK 12
/* CMU_MIF */
#define CLK_FOUT_MEM0_PLL 1
#define CLK_FOUT_MEM1_PLL 2
@@ -396,8 +392,6 @@
#define CLK_SCLK_BUS_PLL_APOLLO 199
#define CLK_SCLK_BUS_PLL_ATLAS 200
#define MIF_NR_CLK 201
/* CMU_PERIC */
#define CLK_PCLK_SPI2 1
#define CLK_PCLK_SPI1 2
@@ -468,8 +462,6 @@
#define CLK_DIV_SCLK_SCI 70
#define CLK_DIV_SCLK_SC_IN 71
#define PERIC_NR_CLK 72
/* CMU_PERIS */
#define CLK_PCLK_HPM_APBIF 1
#define CLK_PCLK_TMU1_APBIF 2
@@ -513,8 +505,6 @@
#define CLK_SCLK_ANTIRBK_CNT 40
#define CLK_SCLK_OTP_CON 41
#define PERIS_NR_CLK 42
/* CMU_FSYS */
#define CLK_MOUT_ACLK_FSYS_200_USER 1
#define CLK_MOUT_SCLK_MMC2_USER 2
@@ -621,8 +611,6 @@
#define CLK_SCLK_USBDRD30 114
#define CLK_PCIE 115
#define FSYS_NR_CLK 116
/* CMU_G2D */
#define CLK_MUX_ACLK_G2D_266_USER 1
#define CLK_MUX_ACLK_G2D_400_USER 2
@@ -653,8 +641,6 @@
#define CLK_PCLK_G2D 25
#define CLK_PCLK_SMMU_G2D 26
#define G2D_NR_CLK 27
/* CMU_DISP */
#define CLK_FOUT_DISP_PLL 1
@@ -771,8 +757,6 @@
#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
#define DISP_NR_CLK 116
/* CMU_AUD */
#define CLK_MOUT_AUD_PLL_USER 1
#define CLK_MOUT_SCLK_AUD_PCM 2
@@ -824,8 +808,6 @@
#define CLK_SCLK_I2S_BCLK 46
#define CLK_SCLK_AUD_I2S 47
#define AUD_NR_CLK 48
/* CMU_BUS{0|1|2} */
#define CLK_DIV_PCLK_BUS_133 1
@@ -840,8 +822,6 @@
#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
#define BUSx_NR_CLK 11
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
@@ -865,8 +845,6 @@
#define CLK_PCLK_SYSREG_G3D 18
#define CLK_SCLK_HPM_G3D 19
#define G3D_NR_CLK 20
/* CMU_GSCL */
#define CLK_MOUT_ACLK_GSCL_111_USER 1
#define CLK_MOUT_ACLK_GSCL_333_USER 2
@@ -898,8 +876,6 @@
#define CLK_PCLK_SMMU_GSCL1 27
#define CLK_PCLK_SMMU_GSCL2 28
#define GSCL_NR_CLK 29
/* CMU_APOLLO */
#define CLK_FOUT_APOLLO_PLL 1
@@ -935,8 +911,6 @@
#define CLK_SCLK_HPM_APOLLO 29
#define CLK_SCLK_APOLLO 30
#define APOLLO_NR_CLK 31
/* CMU_ATLAS */
#define CLK_FOUT_ATLAS_PLL 1
@@ -981,8 +955,6 @@
#define CLK_ATCLK 38
#define CLK_SCLK_ATLAS 39
#define ATLAS_NR_CLK 40
/* CMU_MSCL */
#define CLK_MOUT_SCLK_JPEG_USER 1
#define CLK_MOUT_ACLK_MSCL_400_USER 2
@@ -1016,8 +988,6 @@
#define CLK_PCLK_SMMU_JPEG 28
#define CLK_SCLK_JPEG 29
#define MSCL_NR_CLK 30
/* CMU_MFC */
#define CLK_MOUT_ACLK_MFC_400_USER 1
@@ -1040,8 +1010,6 @@
#define CLK_PCLK_SMMU_MFC_1 17
#define CLK_PCLK_SMMU_MFC_0 18
#define MFC_NR_CLK 19
/* CMU_HEVC */
#define CLK_MOUT_ACLK_HEVC_400_USER 1
@@ -1064,8 +1032,6 @@
#define CLK_PCLK_SMMU_HEVC_1 17
#define CLK_PCLK_SMMU_HEVC_0 18
#define HEVC_NR_CLK 19
/* CMU_ISP */
#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
#define CLK_MOUT_ACLK_ISP_400_USER 2
@@ -1147,8 +1113,6 @@
#define CLK_SCLK_PIXELASYNCS_ISPC 76
#define CLK_SCLK_PIXELASYNCM_ISPC 77
#define ISP_NR_CLK 78
/* CMU_CAM0 */
#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
@@ -1285,8 +1249,6 @@
#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
#define CAM0_NR_CLK 134
/* CMU_CAM1 */
#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1
@@ -1404,12 +1366,8 @@
#define CLK_ATCLK_ISP 111
#define CLK_SCLK_ISP_CA5 112
#define CAM1_NR_CLK 113
/* CMU_IMEM */
#define CLK_ACLK_SLIMSSS 2
#define CLK_PCLK_SLIMSSS 35
#define IMEM_NR_CLK 36
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */

4
include/dt-bindings/clock/exynos7885.h
View File

@@ -69,7 +69,6 @@
#define CLK_GOUT_FSYS_MMC_EMBD 58
#define CLK_GOUT_FSYS_MMC_SDIO 59
#define CLK_GOUT_FSYS_USB30DRD 60
#define TOP_NR_CLK 61
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
@@ -86,7 +85,6 @@
#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12
#define CLK_GOUT_TREX_P_CORE_PCLK 13
#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14
#define CORE_NR_CLK 15
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
@@ -132,7 +130,6 @@
#define CLK_GOUT_SYSREG_PERI_PCLK 41
#define CLK_GOUT_WDT0_PCLK 42
#define CLK_GOUT_WDT1_PCLK 43
#define PERI_NR_CLK 44
/* CMU_FSYS */
#define CLK_MOUT_FSYS_BUS_USER 1
@@ -146,6 +143,5 @@
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
#define CLK_GOUT_MMC_SDIO_ACLK 9
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
#define FSYS_NR_CLK 11
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */

10
include/dt-bindings/clock/exynos850.h
View File

@@ -88,7 +88,6 @@
#define CLK_MOUT_G3D_SWITCH 76
#define CLK_GOUT_G3D_SWITCH 77
#define CLK_DOUT_G3D_SWITCH 78
#define TOP_NR_CLK 79
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
@@ -115,7 +114,6 @@
#define CLK_GOUT_GPIO_ALIVE_PCLK 22
#define CLK_GOUT_PMU_ALIVE_PCLK 23
#define CLK_GOUT_SYSREG_APM_PCLK 24
#define APM_NR_CLK 25
/* CMU_AUD */
#define CLK_DOUT_AUD_AUDIF 1
@@ -179,7 +177,6 @@
#define IOCLK_AUDIOCDCLK6 59
#define TICK_USB 60
#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
#define AUD_NR_CLK 62
/* CMU_CMGP */
#define CLK_RCO_CMGP 1
@@ -197,7 +194,6 @@
#define CLK_GOUT_CMGP_USI1_IPCLK 13
#define CLK_GOUT_CMGP_USI1_PCLK 14
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
#define CMGP_NR_CLK 16
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
@@ -212,7 +208,6 @@
#define CLK_GOUT_G3D_BUSD_CLK 10
#define CLK_GOUT_G3D_BUSP_CLK 11
#define CLK_GOUT_G3D_SYSREG_PCLK 12
#define G3D_NR_CLK 13
/* CMU_HSI */
#define CLK_MOUT_HSI_BUS_USER 1
@@ -231,7 +226,6 @@
#define CLK_GOUT_HSI_PPMU_ACLK 14
#define CLK_GOUT_HSI_PPMU_PCLK 15
#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
#define HSI_NR_CLK 17
/* CMU_IS */
#define CLK_MOUT_IS_BUS_USER 1
@@ -257,7 +251,6 @@
#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
#define CLK_GOUT_IS_SYSREG_PCLK 23
#define IS_NR_CLK 24
/* CMU_MFCMSCL */
#define CLK_MOUT_MFCMSCL_MFC_USER 1
@@ -275,7 +268,6 @@
#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
#define MFCMSCL_NR_CLK 16
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
@@ -312,7 +304,6 @@
#define CLK_GOUT_UART_PCLK 32
#define CLK_GOUT_WDT0_PCLK 33
#define CLK_GOUT_WDT1_PCLK 34
#define PERI_NR_CLK 35
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
@@ -329,7 +320,6 @@
#define CLK_GOUT_SSS_PCLK 12
#define CLK_GOUT_GPIO_CORE_PCLK 13
#define CLK_GOUT_SYSREG_CORE_PCLK 14
#define CORE_NR_CLK 15
/* CMU_DPU */
#define CLK_MOUT_DPU_USER 1

28
include/dt-bindings/clock/imx8-clock.h
View File

@@ -164,4 +164,32 @@
#define IMX_ADMA_LPCG_CLK_END 45
#define IMX_ADMA_ACM_AUD_CLK0_SEL 0
#define IMX_ADMA_ACM_AUD_CLK1_SEL 1
#define IMX_ADMA_ACM_MCLKOUT0_SEL 2
#define IMX_ADMA_ACM_MCLKOUT1_SEL 3
#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4
#define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5
#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6
#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7
#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8
#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9
#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10
#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11
#define IMX_ADMA_ACM_SAI0_MCLK_SEL 12
#define IMX_ADMA_ACM_SAI1_MCLK_SEL 13
#define IMX_ADMA_ACM_SAI2_MCLK_SEL 14
#define IMX_ADMA_ACM_SAI3_MCLK_SEL 15
#define IMX_ADMA_ACM_SAI4_MCLK_SEL 16
#define IMX_ADMA_ACM_SAI5_MCLK_SEL 17
#define IMX_ADMA_ACM_SAI6_MCLK_SEL 18
#define IMX_ADMA_ACM_SAI7_MCLK_SEL 19
#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20
#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21
#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22
#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23
#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24
#define IMX_ADMA_ACM_CLK_END 25
#endif /* __DT_BINDINGS_CLOCK_IMX_H */

2
include/dt-bindings/clock/imx8mp-clock.h
View File

@@ -130,7 +130,7 @@
#define IMX8MP_CLK_SAI1 123
#define IMX8MP_CLK_SAI2 124
#define IMX8MP_CLK_SAI3 125
#define IMX8MP_CLK_SAI4 126
/* #define IMX8MP_CLK_SAI4 126 */
#define IMX8MP_CLK_SAI5 127
#define IMX8MP_CLK_SAI6 128
#define IMX8MP_CLK_ENET_QOS 129

3
include/dt-bindings/clock/imx93-clock.h
View File

@@ -203,6 +203,7 @@
#define IMX93_CLK_ARM_PLL 198
#define IMX93_CLK_A55_SEL 199
#define IMX93_CLK_A55_CORE 200
#define IMX93_CLK_END 201
#define IMX93_CLK_PDM_IPG 201
#define IMX93_CLK_END 202
#endif

1
include/dt-bindings/clock/marvell,mmp2-audio.h
View File

@@ -6,5 +6,4 @@
#define MMP2_CLK_AUDIO_SSPA0 1
#define MMP2_CLK_AUDIO_SSPA1 2
#define MMP2_CLK_AUDIO_NR_CLKS 3
#endif

1
include/dt-bindings/clock/marvell,mmp2.h
View File

@@ -91,5 +91,4 @@
#define MMP3_CLK_SDH4 126
#define MMP2_CLK_AUDIO 127
#define MMP2_NR_CLKS 200
#endif

1
include/dt-bindings/clock/marvell,pxa168.h
View File

@@ -63,5 +63,4 @@
#define PXA168_CLK_SDH01_AXI 111
#define PXA168_CLK_SDH23_AXI 112
#define PXA168_NR_CLKS 200
#endif

3
include/dt-bindings/clock/marvell,pxa1928.h
View File

@@ -36,7 +36,6 @@
#define PXA1928_CLK_THSENS_CPU 0x26
#define PXA1928_CLK_THSENS_VPU 0x27
#define PXA1928_CLK_THSENS_GC 0x28
#define PXA1928_APBC_NR_CLKS 0x30
/* axi peripherals */
@@ -53,6 +52,4 @@
#define PXA1928_CLK_GC3D 0x5d
#define PXA1928_CLK_GC2D 0x5f
#define PXA1928_APMU_NR_CLKS 0x60
#endif

1
include/dt-bindings/clock/marvell,pxa910.h
View File

@@ -55,5 +55,4 @@
#define PXA910_CLK_CCIC0_PHY 108
#define PXA910_CLK_CCIC0_SPHY 109
#define PXA910_NR_CLKS 200
#endif

18
include/dt-bindings/clock/samsung,exynosautov9.h
View File

@@ -166,16 +166,12 @@
#define GOUT_CLKCMU_PERIC1_IP 248
#define GOUT_CLKCMU_PERIS_BUS 249
#define TOP_NR_CLK 250
/* CMU_BUSMC */
#define CLK_MOUT_BUSMC_BUS_USER 1
#define CLK_DOUT_BUSMC_BUSP 2
#define CLK_GOUT_BUSMC_PDMA0_PCLK 3
#define CLK_GOUT_BUSMC_SPDMA_PCLK 4
#define BUSMC_NR_CLK 5
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
#define CLK_DOUT_CORE_BUSP 2
@@ -183,8 +179,6 @@
#define CLK_GOUT_CORE_CCI_PCLK 4
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
#define CORE_NR_CLK 6
/* CMU_FSYS0 */
#define CLK_MOUT_FSYS0_BUS_USER 1
#define CLK_MOUT_FSYS0_PCIE_USER 2
@@ -226,8 +220,6 @@
#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
#define FSYS0_NR_CLK 37
/* CMU_FSYS1 */
#define FOUT_MMC_PLL 1
@@ -251,8 +243,6 @@
#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
#define FSYS1_NR_CLK 19
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
@@ -262,8 +252,6 @@
#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6
#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7
#define FSYS2_NR_CLK 8
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_BUS_USER 1
#define CLK_MOUT_PERIC0_IP_USER 2
@@ -308,8 +296,6 @@
#define CLK_GOUT_PERIC0_PCLK_10 42
#define CLK_GOUT_PERIC0_PCLK_11 43
#define PERIC0_NR_CLK 44
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
#define CLK_MOUT_PERIC1_IP_USER 2
@@ -354,14 +340,10 @@
#define CLK_GOUT_PERIC1_PCLK_10 42
#define CLK_GOUT_PERIC1_PCLK_11 43
#define PERIC1_NR_CLK 44
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
#define CLK_GOUT_SYSREG_PERIS_PCLK 2
#define CLK_GOUT_WDT_CLUSTER0 3
#define CLK_GOUT_WDT_CLUSTER1 4
#define PERIS_NR_CLK 5
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */